Client:Our client a leading Multinational Semiconductor Organisation requires Senior Principal SoC IP Design Verification Engineer for role based in Cambridge, England.

Role:The group develops and licenses IP for system designs. This includes CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. The IP designs are used by most of the top semiconductor vendors today, and our customers are shipping billions of chips annually using our components.The Engineering team seeks an experienced and talented SoC design verification engineer. In this role, you will be responsible for developing and validating reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications.This is a technically rewarding role with high visibility within the organisation. The group will also implement reference designs on emulation systems and support applications for product demonstrations.This role requires extensive experience IP integration and implementing SoC and compute-based systems. You will work closely with compute and interface IP development engineering and build designs to demonstrate the capabilities ofsubsystems and components.Responsibilities:Develop, implement, and debug SoC reference systems.Integrate compute, memory and interface IP in system designs.Analyse IP products and implementation flows.Identify gaps and work with development teams to improve products.Develop collateral, and training material for CSG system customers.Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team’s workflows.Education:BS in Electronic Engineering/Computer Science

Experience:

8+ years work experienceMust have at least 3 years of experience in ASIC design, integration, or verification.Must have expertise in some of the following domains: processor design, on-chip communication and interconnects, high-speed interfaces, or chiplets.Expertise in Verilog/System Verilog for coding and verification.Proficiency in RTL design techniques, including synthesis, timing closure, and verification.Experience in using UVM for functional verification of ASIC designs.Experience with EDA tools like Cadence and Synopsys for design simulation and verification.Extensive experience with FPGA emulation, design tools, and verification.Contact:

For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie#J-18808-Ljbffr