Senior SoC Design Verification Engineer

Job Title - Senior SoC Design Verification EngineerLocation: Cambridge/Bristol UK,Employment Type: Contract (Inside Ir35). Role OverviewWe are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design.Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on Embedded processor cores. The role requires strong debugging and analytical skills, an understanding of ARM processor based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements. Key Responsibilities- 1. Subsystem and SoC Functional Verification2. System Verilog/UVM Testbench Reuse and Enhancement3. Processor-Based C Test Development and Verification4. Regression Execution, Debugging, and Coverage Closure5. Verification Planning and Collaboration Required Technical Skills Essential Skills Strong hands-on experience in digital design verification using System Verilog and UVM. Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components. Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers. Experience in subsystem-level or SoC-level functional verification. Strong understanding of SoC ..... full job details .....