SoC Design Verification Engineer

SoC Design Verification Engineer Job Title: SoC Design Verification Engineer/Senior Design Verification EngineerLocation: Bristol andamp; Cambridge, UKNumber of Positions: 20 (10 Bristol/10 Cambridge)Contract Duration: 6 monthsRate: £55 per hour (Inside IR35)Working Model: Hybrid - 3 days onsite and 2 days remoteExperience: 5-20 YearsNotice Period: Immediate or maximum 2 weeks Job Overview We are looking for experienced SoC Design Verification Engineers to join Synopsys Inc. for a next-generation multi-die System-on-Chip (SoC) project. The successful candidates will work on subsystem-level and SoC-level functional verification using SystemVerilog and UVM methodologies. The role also involves processor-based verification through Embedded C test programs running on processor cores. Candidates should have strong debugging skills, hands-on UVM experience and the ability to enhance and maintain existing verification environments. Key Responsibilities Perform subsystem-level and SoC-level functional verification. Develop, modify and debug SystemVerilog/UVM testbenches. Develop and execute Embedded C test programs for processor-based SoC verification. Execute regression tests, analyse failures and resolve simulation issues. Perform functional coverage analysis and drive coverage closure. Debug complex RTL simulation failures using waveform tools. Work with design teams to understand design changes and update verification environments. Support verification planning ..... full job details .....